Data transfer control method, and peripheral circuit, data processor and data processing system for the method

ABSTRACT

A memory  1  performs its internal operation in response to access requests ( 200, 201  and  202 ) of a CPU  2  in synchronism with the oscillated output of a self-excited oscillator  102  incorporated therein and according to said access requests, and outputs a response request  103  for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request  103  from the accessed memory and according to the kinds of said access requests.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method of controlling thetransfer of a variety of information such as instruction information ordata information between a memory or a peripheral circuit and a dataprocessor, and a peripheral circuit, a data processor and a dataprocessing system using the method, and, more particularly, to atechnique which is especially effective if applied to the controltechnique of the data transfer between the data processor and a memory.Incidentally, the data processor in the present Specification will coverthe general concept of a CPU (i.e., Central Processing Unit), amicroprocessor, a microcomputer, a single-chip microcomputer, adigital-signal processor or a direct memory access controller.

SUMMARY OF THE INVENTION

[0002] Some RISC processors of the prior art include one or more cachememories in a chip from the point of view of performance, cost,manufacture process and technical level of the LSI. Such a CPU isconnected with a number of memories and input/output) circuits on acircit board to construct a system. It is usual to use an operationclock (or system clock) as a reference to the operation of the system.Usually, the peripheral circuits such as the memories and theinput/output circuits to constitute the system are individually givendifferent functions and characteristics to have individually differentoperating procedures, response times or operating speeds. It is needlessto say that the CPU interfaces owned by the memories and theinput/output circuits are frequently different from one another althoughthey have some similarity in the functions or timings.

[0003] As to the differences in such functions, operating speeds andinterface specifications, memory controllers are used for the memories,and I/O controllers are used for the input/output circuits. Thesecontrollers have functions, as roughly divided into the following twopoints.

[0004] The first function is to inform the memories and the input/outputcircuits of which memory or input/output circuit is selected by the CPU,and initiates a data transfer. This function can be regarded as theso-called “chip selection” or “chip enable control”. For example, logicoperations between the signals indicating the kinds of addressing andaccess are carried out to produce pulses or level signals by using anoperation clock or the like thereby to activate only the memory selectedor the signal connected with the input/output circuit.

[0005] The second function is to count the operation clocks by a counterthereby to produce a signal demanding the CPU for an extension of theaccess period at the unit of the operation clock for the wait or readyoperation. Under to the rule of confirming the signal for each operationclock by the CPU, the difference in the timing or the operation speedbetween the CPU and the memory or the peripheral circuit is absorbed torealize the data transfer without fail. This function is the so-called“wait state control function”.

[0006] However, we have revealed that the aforementioned wait statefunction by the controller has the following problems.

[0007] (1) Since the duration of the data transfer time to be extendedby the wait state is always determined at the operation clock unit ofthe system, it is impossible to sufficiently extract the performanceintrinsic to the memory or peripheral circuit. Moreover, it issubstantially impossible to design the system by using the performance,which is based upon the design data submitted by the maker/seller as tothe memory or the input/output circuit, in the limit state. Since acertain operation margin is considered, a data transfer involves idletime in most cases so that the data transfer efficiency on the data busdecreases. This problem applies not only to the case in which the systemis constructed on a circuit board, i.e., in which the connectionsbetween the memories or the input/output circuits and the CPU are madethrough the buses on the board, but also to the case in which the CPUand the memories are formed over a common semiconductor chip.Specifically, if an optimum design were to made considering the electriccharacteristics and the arrangement of circuit elements, the controllersand the memories could effect the data transfer efficiently to theoperation clock of the controllers. In the actual circuit design,however, a delicate timing has to be made in the chip although not easy,while considering the characteristics of the individual logic circuitblocks.

[0008] (2) The aforementioned wait state control takes serious troublesbecause the designer has to design the system for the individualmemories or input/output circuits, if in plurality, due to thedifferences in the functions (including the protocol) and performances.

[0009] (3) The circuit portions required for the wait state control haveto cover the sets of memories and input/output circuits, thus causingdifficulties in the high speed, the small size and the low prices suchas the complicatedness of the system, the increase in the part number orthe increase in the load upon the signal line.

[0010] (4) As has been described in the aforementioned problem (1), thewait state control cannot sufficiently extract the performancesintrinsic to the memories and the peripheral circuits so that it limitsthe speed-up of the operations. In order to eliminate this limit,therefore, all or the highly efficient memories or input/output circuitscould be connected without the wait state control. If, however, theoperation clock of the controller is suppressed according to thecharacteristics such as the operation speed of the memories and theinput/output circuits, the controller such as the CPU has a tendency tohave its operation clock speeded up to drop the value of the system. If,on the contrary, a fast memory or input/output circuit is to be used inconformity to the operation clock of the controller, an extremely highrise is caused in the system price.

[0011] Thus, the system of the prior art for producing the timing of thedata transfer between the CPU and the peripheral circuit from theoperation clock of the CPU or the system cannot realize the datatransfer which can sufficiently exploit the intrinsic performance of theperipheral circuit such as the memory. Specifically, we have thought itdifficult to desire a basic development to a high speed if the CPU andthe peripheral circuit are connected by the wait state control functionwhich stresses the reliable operation by returning the wait signal tothe CPU at a timing of integer times as high as that of the operationclock on the basis of the characteristics of the peripheral circuit.

[0012] An object of the present invention is to provide a techniquewhich is enabled to effect a data transfer by sufficiently exhibitingthe intrinsic characteristics owned by a peripheral circuit such as amemory.

[0013] Another object of the present invention is to provide aperipheral circuit for producing a timing of the data transfer accordingto its own characteristics.

[0014] A further object of the present invention is to provide a dataprocessor capable of transferring data efficiently with such peripheralcircuit.

[0015] A further object of the present invention is to provide a dataprocessing system capable of transferring data fast with the dataprocessor by sufficiently exhibiting the intrinsic characteristics ownedby the peripheral circuit such as the memory.

[0016] The aforementioned and other objects and novel features of thepresent invention will become apparent from the following description tobe made with reference to the accompanying drawings.

[0017] A representative of the invention to be disclosed herein will bebriefly described in the following.

[0018] Specifically, as represented in FIG. 1, a memory (1) acting as aperipheral circuit performs its internal operation in accordance withaccess requests (200, 201 and 202) from a CPU (2) exemplifying the dataprocessor, and in synchronism with the output signal of a self-excitedoscillator (102) incorporated therein; and outputs a response requests(103) to the data processor in synchronism with that internal operationin response to the access requests.

[0019] The data processor sends an access request to a desiredperipheral circuit; and transfers data to or from the peripheral circuitdepending on the type of the access request in synchronism with aresponse request received from the peripheral circuit.

[0020] The control of the data transfer between the data processor andthe peripheral circuit comprises the steps of sending an access requestto the peripheral circuit from the data processor; allowing theperipheral circuit to perform its internal operation according to theaccess request in synchronism with the output signal of a self-excitedoscillator incorporated therein; sending a response to the peripheralcircuit from the data processor in synchronism with its internaloperation in response to the access request; and transferring data to orfrom the data processor depending on the type of the access request insynchronism with said response request.

[0021] In order to realize the aforementioned means with the minimumnumber of circuits to be added to the construction of the existing dataprocessor or peripheral circuit, the access requests can contain theinformation (200 and 201) for indicating that the peripheral circuit isselected as the object to be accessed and the data transfer direction,and the response request can contain the signal (103) to be changed insynchronism with the internal operation of the peripheral circuit.

[0022] In order to construct the peripheral circuit having theaforementioned functions relatively simply, as representatively shown inFIG. 5, the peripheral circuit includes a cycle timing generator (1010)for producing an access cycle signal (1013) of the internal operation inresponse to the access request from the data processor and on the basisof an output signal of the self-excited oscillator (102); an externalterminal (AC) for outputting the access cycle signal as the responserequest to the outside; and an internal timing generator (1011) forproducing an internal operation timing signal in synchronism with theaccess cycle signal (103).

[0023] In case such peripheral circuit is constructed as a burstreadable memory (capable of reading a continuous data of a plurality ofwords), there may be added a counter (or burst counter) (105) forcounting the number of continuous data read words from the memory cellarray on the basis of the change in the access cycle signal to stop theoscillations of the self-excited oscillator when the counted resultreaches a predetermined count value, as representatively shown in FIG.6. At this time, in order to set the number of continuous data readwords programmably, the counter is equipped with a parameter register(1051) for latching the predetermined count value presettably from theoutside, as representatively shown in FIG. 12. This parameter registercan be positioned such that in case the counter has storage stagescorresponding to its bit count, the memory stages are used as asubstantial parameter register in a presettable manner.

[0024] In order to transfer data at different transfer rates quickly andefficiently between the internal unit and the outside, the dataprocessor having the aforementioned functions is equipped, asrepresentatively shown in FIG. 8, with a buffer memory (206) whichincludes: a asynchronous port (2064) for writing/reading on the basis ofthe response request; and a synchronous port (2065) for writing/readingin synchronism with the internal operation clock. The synchronous portof the buffer memory is connected as the internal unit to an arithmeticunit or register, and the asynchronous port of the buffer memory isconnected with an input/output buffer circuit (205) to be interfacedwith the outside. At this time, in order that the data transferred fromthe peripheral circuit to the buffer memory may be quickly used for theoperation of an internal unit (204), the buffer memory may be equippedwith a counter circuit (2066) for counting the number of continuous readaccesses, which are sent to the peripheral circuit from the accesscontrol circuit, in terms of the number of changes in the responserequest, so that the resultant detection result may be fed as theinformation meaning the complete of the read data acquisition by saidaccess request (i.e., the output information of an AND gate 2063R5, asrepresentatively shown in FIG. 9) to the central processing unit. Thebuffer memory should not be limited to a perfect dual port but may beused as an apparent dual port for operating a unit-port buffer memory ina time sharing manner.

[0025] When the data processor is interfaced with a plurality ofperipheral circuits of different kinds, one input terminal of the dataprocessor for response request is connected through an OR gate or awired OR so that it may be shared among the output terminals of eachperipheral circuit for the response request, as representatively shownin FIG. 14.

[0026] In order that mutually identical peripheral circuits having amulti-bit input/output function of ½n bits for the number of bits of thedata bus may be interfaced with the data processor, the data processormay be provided with a plurality of sets of buffer memories (206U and206L) each having: an asynchronous port for writing/reading in responseto the response request; and a synchronous port for writing/reading insynchronism with the internal operation clock, as representatively shownin FIG. 13.

[0027] According to the means described above, the peripheral circuit isoperated synchronously with the output signal of the self-excitedoscillator intrinsic thereto but asynchronously from the operation clocksignal of the data processor requesting access to the peripheralcircuit. In this relation, the mutual interface of data is realized bythe mutually equivalent access requests and the response requests forthe former. As a result, the time period for the series of datatransfer, which as been limited to integer times as high as that of thefundamental operation clock of the data processor of the prior art, isdetermined according to the clock cycle of the response requestdepending upon the intrinsic self-excited oscillation frequency which isproduced according to the characteristics such as the operation speed ofthe peripheral circuit such as the memory. As a result, the datatransfer can be easily realized for the individual characteristic limittime periods of the peripheral circuit and the data processor. In otherwords, it is possible to reduce the spare time period which has beenestablished for synchronization with the operation clock of the dataprocessor, as has been troubled in the prior art. Moreover, the waitstate control circuit for the interface between the data processor andeach peripheral circuit can be dispensed with to simplify the circuitconnecting means.

[0028] The data processor equipped on-chip with the buffer memory to beinterfaced with the peripheral circuit can internally absorb thedifference in the data transfer rate between the internal unit of thedata processor and the outside to require no sequential wait time forreading/writing the data in response to the access request.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a system block diagram showing a CPU according to oneembodiment of a data processor of the present invention and a memoryaccording to one embodiment of a peripheral circuit of the presentinvention;

[0030]FIG. 2 is a timing chart showing one example of data transferoperations in the system of FIG. 1;

[0031]FIG. 3 is a block diagram showing a system making a data transferpossible through a wait state control unit with reference to theembodiment of FIG. 1;

[0032]FIG. 4 is a timing chart of the data transferring operations ofFIG. 3;

[0033]FIG. 5 is a block diagram showing one embodiment of the memory ofFIG. 1;

[0034]FIG. 6 is a circuit diagram showing one detailed example of acycle timing generator of FIG. 5;

[0035]FIG. 7 is a operation timing chart of one example of the memory ofFIG. 6;

[0036]FIG. 8 is a block diagram of one detailed embodiment of the CPU ofFIG. 1;

[0037]FIG. 9 is a block diagram of one detailed example of a circuitportion relating to a read buffer in the buffer control circuit of FIG.8;

[0038]FIG. 10 is a block diagram of one detailed example of a circuitportion relating to a write buffer in the buffer control circuit of FIG.8;

[0039]FIG. 11 is a block diagram showing one embodiment of a CPU havinga buffer memory of the type sharing a read buffer and a write buffer;

[0040]FIG. 12 is a block diagram of one embodiment of a memory in whicha burst counter is equipped with a parameter register;

[0041]FIG. 13 is a block diagram of one embodiment when identicalmemories having a function to input/output multiple bits of ½n times,for example, as large as the bits of a data but are interfaced with theCPU;

[0042]FIG. 14 is a block diagram of one embodiment of the case in whichmemories having different characteristics/functions are mixed toconstruct a system; and

[0043]FIG. 15 is an overall block diagram of one embodiment of a dataprocessing system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044]FIG. 1 shows a CPU according to one embodiment of a data processorof the present invention and a memory according to one embodiment of aperipheral circuit of the present invention such that the CPU and thememory are connected.

[0045] A memory 1, as shown in FIG. 1, is formed on a semiconductorsubstrate and includes a memory cell array 100 and an access cyclecontrol unit 101, as representatively illustrated. In response to accessrequests (200, 201 and 202) from a CPU 2, the memory 1 performs readoperations or write operations in synchronism with an oscillation outputsignal of a self-excited oscillator 102 incorporated therein, andoutputs a response request (103) responding to the access requests tothe CPU 2 in synchronism with its internal operations.

[0046] The CPU 2, as shown in FIG. 1, is formed on a semiconductorsubstrate and includes an arithmetic circuit 204; a buffer memory 206having its one port coupled to the arithmetic circuit 204; aninput/output buffer circuit 205 coupled to the other port of the buffermemory 206 and an external data bus 211; an access control circuit 207for sending access requests to the external memory 1 and otherperipheral circuits (not shown); and a central control unit 208 forcontrolling the entire operations of the central processing unit such asan instruction executing sequence control circuit or an interruptcontrol circuit. The CPU 2 sends the access requests (200, 201 and 202)to a desired peripheral circuit such as the memory 1 and receives theresponse request (103) of the peripheral circuit such as the memory 1 tolatch the data in the buffer memory 206 from the outside or to outputthe data from the buffer memory 206 to the outside in synchronism withthe response request and according to the kind of said access request.The memory 1 is operated in synchronism with the output signal of itsown self-excited cillator 102. On the other hand, the CPU 2 is operatedin synchronism with an operation clock 209 of the system.

[0047] In case the CPU 2 gains access to the memory 1, the start of thisaccess is transmitted to the memory 1 by the access start signal 200.This access start signal 200 is deemed as a signal equivalent to a chipselecting signal by the memory. According to the present embodiment, theaccess control circuit 207 has a function as a chip selectingcontroller, although not especially limited thereto. This function canbe replaced by a decoder for decoding several more significant bits ofthe address signal outputted from the CPU 2 to the outside, to producethe chip selecting signal. In any case, reference is made to both anaddress assigned to the peripheral circuit to be accessed and an addressto be made in the CPU 2. In this sense, an access request to theperipheral circuit such as the memory, such as an instruction of theaccess start is sent directly or indirectly by a circuit portion formaking the access address, and the access control circuit is understoodto contain such circuit portion.

[0048] The direction of data transfer is instructed by theread/{overscore (write)} signal 201. The “read” means the data transferfrom the peripheral circuit such as the memory 1 to the CPU 2, and the“write” means the data transfer from the CPU 2 to the peripheral circuitsuch as the memory 1. According to the present embodiment, the locationof the data in the peripheral circuit, as requested for access, isdesignated by the address signal fed to an address bus 210. The numberof words for data transfer is instructed by the instruction signal(i.e., single/{overscore (burst)} signal) 202 in a single mode/burstmode. Without the burst mode or the continuous data transfer mode, thesingle/{overscore (burst)} signal 202 can be eliminated.

[0049] Upon detecting the access request in terms of the access startsignal 200, the access cycle control unit 101 produces the internalaccess cycle signal on the basis of the output signal of theself-excited oscillator 102. Inside of the memory 1, the read or writeoperations instructed by the read/{overscore (write)} control signal 201are performed in synchronism with the access cycle signal. Outside ofthe memory 1, moreover, this access cycle signal is outputted as theaccess clock signal 103 to the CPU 2. This access clock signal 103 is aclock signal intrinsic to the memory 1 and is fed to the CPU 2 as theresponse request in response to the access request from the CPU 2.

[0050]FIG. 2 shows the relations between the data output of the memory 1in the read operation and the data output timing of the CPU 2 in thewrite operation, and the access clock signal 103. According to FIG. 2,when instructed to perform the read operation, the memory 1 outputs, thedesired data to the data bus 211 at a timing for ensuring a setup time(Trs)/a hold time (Trh) for the rising edge of the access clock signal(or the access cycle signal in the memory). That data is latched by theCPU 2 in the buffer memory 206 at the rising edge of the access clocksignal 103. In the writing operation, the CPU 2 outputs the data fromthe buffer memory 206 to the data bus 211 so as to ensure a setup time(Tws)/hold time (Twh) for the fall of the access clock signal 103. Thememory 1 latches that data at the falling edge of the access cyclesignal. Incidentally, the write operation can refer to the rise of theaccess clock signal 103.

[0051] According to the embodiment of FIG. 1, the access cycle controlunit 101 outputs a cycle complete signal 104 for informing the CPU 2 ofthe complete of the continuous data transfer in the burst mode. In theaccess control unit 101, the number for words transferred is counted bya burst counter 105 in terms of the access cycle signal equivalent tothe access clock signal 103 so that the count-up state is outputted asthe cycle complete signal 104. This cycle complete signal 104 may bereplaced by an identical function at the side of the CPU 2.Specifically, a burst counter for counting the access clock signal 103may be disposed at the side of the CPU 2.

[0052]FIG. 3 is a block diagram showing a system making a data transferpossible through a wait state control unit, in comparison with theforegoing embodiment, and FIG. 4 shows a data transfer timing of thesystem.

[0053] In case a CPU 400 is to transfer data to an external memory 401,as shown in FIG. 3, the start of this data transfer is noticed in termsof an access start signal 403 to the memory 401 and a wait state controlunit 402. Upon reception of the access start signal 403, a read or writeoperation is started according to a read/{overscore (write)} signal 405by a read/write control circuit 404. In synchronism with this, the waitstate control unit 402 also interprets the access start signal 403 andthe read/{overscore (write)} signal 405 and starts the counting of await counter 408 to produce a wait signal 407 for indicating an accesscomplete on the basis of an operation clock 406 identical to that of theCPU 400. In the reading operation, the memory 401 can output the data tobe read to a data bus 409 after a time period guaranteed by itsmaker/seller has elapsed. In the write operation, the memory 401 canlatch the data of the data bus 409 outputted by the CPU 400, after thetime period guaranteed by its maker/seller has elapsed. The complete ofthe read operation or write operation after lapse of the time periodguaranteed by the maker/seller is usually transmitted to the CPU 400 interms of a change of the wait signal 407 to a False in synchronism withthe operation clock 406 of the CPU 400 (or the wait signal is confirmedat the CPU side in synchronism with the operation clock in case it is anasynchronous signal). If the wait signal is set in the read operation tothe false (or a low level) at a time t1, as shown in FIG. 4, the CPUreads the data from the data bus. If the wait signal is set in the writeoperation to the false (or the low level) at a time t2, the CPU confirmsthat the data to be written has been latched in the memory, and stopsthe outputting of the write data.

[0054] It is apparent from the timings of FIG. 4 that the locations (ortimings) of setting the wait signal to the false are usually differentbetween the read cycle and the write cycle. In the burst mode, moreover,the wait signal should naturally be cyclically produced in series oftransfer words, in which the interval of occurrence of a first word isdifferent from those of second and later words. As a result, the CPU 400completes a series of read or write cycles, when it confirms the changein the wait signal 407, to keep the access control circuit 410 in thestandby state till the next cycle starts. Moreover, a changing time, asindicated at Tdis in FIG. 4, is required when the read cycle and thewrite cycle in the identical operation mode are to be interchanged. Thisis because the wait signal is confirmed in synchronism with the clock.Thus, the data transfer making use of the wait signal has to take acomplicated control and an unnecessary time period.

[0055] The following operational effects can be obtained according tothe embodiment thus far described.

[0056] (1) In the present embodiment shown in FIGS. 1 and 2, thelocations of starting the production of the access cycle by theperipheral circuit such as the memory and the timings for updating thechanges are usually different between the read cycle and the writecycle, but the CPU may be dedicated to the inputting/outputting of datain accordance with the change in the access clock signal 103 withoutconsidering any of those complicated timings. In short, the datatransfer at the complicated timings can be realized without the waitstate control unit which has been indispensable in the prior art. Thisrealization naturally covers both the single transfer and the bursttransfer.

[0057] (2) Without the wait state control unit, the data transfer can beachieved by the access clock signal outputted from the peripheralcircuit such as the memory, to reduce the access cycle time period andimprove the bus using efficiency. Specifically, the peripheral circuitsuch as the memory is operated in synchronism with the output signaloscillated by its own self-excited oscillator 102 and asynchronously ofthe operation clock signal 209 of the CPU which sends an access requestto that peripheral circuit, so that the interface between their data isrealized the mutually equivalent access requests and the responserequests to the access requests. As a result, a series of data transfertime periods, which have been limited in the prior art to an integertimes as high as the fundamental operation clock of the data processorsuch as the CPU, can be determined according to the clock cycle of theresponse request depending upon the intrinsic self-excited oscillationfrequency which is produced according to the characteristics such as theoperating speed of the peripheral circuit such as the memory. As aresult, it is easy to realize the data transfer for the limit timeperiods of the individual characteristics of the peripheral circuit andthe CPU. In other words, it is possible to reduce the unnecessary timeperiod which has been consumed for synchronization with the operationclock of the CPU, as has been troubled in the prior art.

[0058] (3) The CPU 2 is equipped on the common chip with the buffermemory 206 to be interfaced with the peripheral circuit so that thedifference in the data transfer rate between the internal unit 204 ofthe CPU and the outside can be internally absorbed to prevent anysequential standby between the time periods for processing the read dataand the write data by the access request.

[0059] (4) The data transfer type according to the foregoing embodimentcan be widely interpreted to give a bus right to the memory if locallyconsidered. Specifically, it is thought that the system operates withthe operation clock 209 of the CPU 2 at the start of the data transferbut with the operation clock 103 of the memory during the data transfer,and the but right seems to be dynamically transferred. This concept isthought to have an effective meaning especially when the degree ofintegration of the LSI is improved in the future so that the logicfunction merges into the memory.

[0060]FIG. 5 is a block diagram showing one embodiment of theaforementioned memory. The memory 1, as shown in FIG. 5, is formed as astatic random access memory (i.e., SRAM) over one semiconductorsubstrate made of single crystalline silicon by the well-knownsemiconductor integrated circuit manufacturing technique, although notespecially limited thereto.

[0061] The shown memory 1 includes input terminals ARO to ARm of a rowaddress signal; input terminals ACO to ACn of a column address signal;data input/output terminals I/OO to I/Op; a chip select signal inputterminal CS; an output enable signal input terminal OE; a write enablesignal input terminal WE; an access cycle signal output terminal AC; aburst/single change signal input terminal B/S; and a supply terminal(not shown). In connection with FIG. 1: the chip select signal inputterminal CS is fed with the access start signal 200; the output enablesignal input terminal OE is fed with a read signal composing theread/{overscore (write)} signal 201; the write enable signal inputterminal WE is fed with a write signal composing the read/{overscore(write)} signal 201; and the access cycle signal 103 is outputted fromthe access cycle signal output terminal AC.

[0062] The memory cell array 100 includes static memory cells arrangedin a matrix, whose select terminals are connected through word lines tothe outputs of a row address decoder 110. This row address decoder 110receives and decodes the internal complementary address signal, which isconverted from the row address signal fed from the out side and areoutputted from a row address buffer 111, to drive one word correspondingto the row address signal, to a select level. The bit lines connected tothe data input/output terminals of the memory cells are commonlyconnected with a common data line 113 through a column switch circuit112. The selection of the bit line to be connected to the common dataline 113 is accomplished by the column switch circuit 112 in response tothe output of a column address decoder 114. This column address decoder114 receives and decodes the internal complementary address signal,which is converted from the column address signal fed from the outsideand is outputted from a column address buffer 115, to select the bitline by the column switch circuit 112. Reference numeral 116 designatesa sense amplifier and an output buffer circuit for amplifying the dataread from the memory cells to the common data line 113 and outputtingthe amplified data to the outside. The sense amplifier and output buffercircuit have their input connected to the common data line 113 and theiroutput connected to the data input/output terminals I/OO to I/Op.Numeral 117 designates an input buffer for inputting the write data fedto the data input/output terminals I/OO to I/O, and the input buffer 117has its output connected to the common data line 113. Numeral 118designates either latch circuit or a data control circuit for equalizingor precharging the common data line.

[0063] The access control unit 101 is equipped with a cycle timinggenerator 1010 and an internal timing generator 1011. This internaltiming generator 1011 is connected to the input terminals CS, OE, WE andB/S to determine the internal operation mode by detecting the accessstart, deciding the read/write operation and deciding the burstmode/single mode, to produce an internal operation timing signalcorresponding to the operation mode in synchronism with the access cyclesignal fed from the cycle timing generator 1010. On the basis of theinstruction of the access start signal fed from the CS terminal, thecycle timing generator 1010 produces a cycle timing signal 1013 and theaccess clock signal 103 in synchronism with the signal fed from theinternal timing generator 1011 on the basis of the output signal fromthe self-excited oscillator 102. Incidentally, a delay circuit 1014 isused to adjust the phase of the self-excited oscillating output, and adelay circuit 1015 is used to match the phases of the access clocksignal 103 outputted from the outside and the cycle timing signal 1013.

[0064]FIG. 6 shows one detailed example of the cycle timing generator1010. The self-excited oscillator 102 has a feedback loop composed of atwo-input AND gate 1020 and an inverter amplifier 1021 for feeding backthe output of the AND gate 1020 to one of the inputs of the same ANDgate 1020, although not especially limited thereto, and a trigger forcontrolling the oscillation and its stop is connected with the otherinput of the AND gate 1020. The trigger circuit is equipped with an ANDgate 1024, to which is inputted the output of a selector 1022 to be setto a high level at an initial state and to which is fed back the outputof an OR gate 1023. This OR gate 1023 receives both the output of theAND gate 1024 and a trigger signal 1025 such as a one-shot pulse to befed in synchronism with the read or write operation from the internaltiming generator 1011, and feeds its output to the AND gate 1020.Incidentally, reference numerals 1026 to 1028 designate waveform shapingelements (or delay elements). This self-excited oscillator 102 outputs alow level in the initial state. When the trigger signal 1025 is changedin this state by the one-shot pulse, oscillations are established in thefeedback loop which is composed of the AND gate 1020 and the inverteramplifier 1021. This oscillating state is continued till the output ofthe selector 1022 is changed into pulses at the low level to set theoutput of the OR gate 1023 to the low level.

[0065] In the construction of FIG. 6, the burst counter 105 and theselector 1022 are used to stop the oscillator. The selector 1022 is fedwith either the B/S signal or an equivalent internal signal to selectthe output of the waveform shaping element 1027 in the single mode.Thus, in the single mode, the self-excited oscillator 102 stops theoscillating operation by changing the access clock signal 103 and thecycle timing signal 1013 by one cycle. In the burst mode, the output ofthe burst counter 105 is selected. This burst counter 105 counts thenumber of data words read continuously from the memory cell array on thebasis of the change in the output pulses of the waveform shaping element1027, and outputs a one- shot pulse which will change from the highlevel to the low level such that the counted result reaches apredetermined value (i.e., a target number of words for burst transfer).As a result, the oscillating operation of the self-excited oscillator102 is stopped when the access cycle corresponding to the target numberof words in the burst mode is established.

[0066]FIG. 7 shows one example of the operation timing chart of thememory of FIG. 6. As shown, in the read cycle, the access cycle signaloutput terminal AC is changed in synchronism with the timing at whichthe read data is outputted. In the write cycle, on the other hand, thewrite data is fed from the CPU in synchronism with the timing at whichthe access cycle signal output terminal AC is changed.

[0067]FIG. 8 is a block diagram showing one detailed embodiment of theCPU 2. The CPU 2, as shown, is formed on a semiconductor substrate madeof single-crystal silicon, by the well-known semiconductor integratedcircuit manufacturing technique, although not limited thereto. The samecircuit blocks as those of FIG. 1 are designated at the same referencecharacters, and their detailed description will be omitted. Here, thebuffer memory 206 will be described in detail.

[0068] The buffer memory 206 is composed of a read buffer 2061, a writebuffer 2062 and a buffer control circuit 2063 of the FIFO (i.e.,First-IN First-Out) type. The read buffer 2061 is dedicated to the datatransfer in the read direction by the CPU, and the write buffer isdedicated to the data transfer in the write direction by the CPU. Bothbuffers 2061 and 2062 are equipped with an asymmetric port 2064 to becontrolled on the basis of a request request fed from the memory 1 inresponse to the access clock signal 103; and a synchronous port 2065 tobe controlled in synchronism with the internal operation clock 209. Thebuffer control circuit 2063 is equipped with an asynchronous controlunit 2063A for controlling the asynchronous port 2064; and a synchronouscontrol unit 2063B for controlling the synchronous port 2065. Theasynchronous port 2064 is connected to the input/output buffer circuit205, and the synchronous port 2065 can be interfaced with the registergroup, the cache memory and so on contained in the arithmetic circuit204.

[0069] The asynchronous control unit 2063A feeds the write buffer 2062with the asynchronous read signal for instructing the read operation andthe asynchronous read address (or pointer) of that time, in synchronismwith the aforementioned change in the access clock signal 103. Insynchronism with this change in the access clock signal 103, moreover,the read buffer 2061 is fed with the asynchronous write signal forinstructing the write signal and the asynchronous write address (orpointer) of that time. A choice between the read buffer 2061 and thewrite buffer 2062 to be accessed in synchronism with the change in theaccess clock signal 103 depends on the information from the centralcontrol unit 208 indicating whether the CPU 2 requests reading orwriting corresponding to the access clock signal 103.

[0070] The synchronous control unit 2063B is operated as a part of theinstruction execution control in the central control unit 208. When thememory read operation is required according to the execution of a datatransfer instruction such as a load instruction, a store instruction ora move instruction, the read buffer 2061 is fed with the synchronousread signal for instructing the read operation and the synchronous readaddress (or pointer) of that time, in synchronism with the operationclock 209. When the memory write operation is required according to theexecution of the data transfer instruction, on the other hand, the writebuffer 2062 is fed with the synchronous write signal instructing thewrite operation and the synchronous write address (or pointer) of thattime, in synchronism with the operation clock 209. A choice between theread buffer 2061 and the write buffer 2062 to be accessed depends on theinstruction decoding signal outputted from the central control unit 208in accordance with the instruction execution.

[0071] The memory 1 of the example of FIG. 8 does not have the functionof producing the cycle complete signal 104. A similar function isexecuted by a burst counter 2066, in the asynchronous control unit 2063Ato feed the burst transfer cycle complete to the access control circuit207. In the CPU 2 of the present embodiment, the count-up signal of theburst counter 2066 is also used for informing the central control unit208 of the write complete in the read buffer 2061 and the read completefrom the write buffer 2062. This operation will be described withreference to FIG. 9.

[0072]FIG. 9 is a detailed block diagram of one example of a circuitportion relating to the read buffer 2061 in the buffer control circuit2063. The synchronous read address of the read buffer 2061 is producedby an upcounter 2063R1, and the asynchronous write address of the readbuffer 2061 is produced by an upcounter 2063R2. The upcount operation ofthe upcounter 2063R2 is performed in synchronism with the timing atwhich the access clock signal 103 is changed to the high level and atwhich the read buffer write signal from the central control unit 208 isactivated. The up count operation of the upcounter 2063R1 is performedin synchronism with the operation clock 209 when the read buffer readsignal from the central control unit 208 is activated. Both theupcounters 2063R1 and 2063R2 are cleared to 0 by the high-level outputof the AND gate 2063R3. It is the clearing timing when the outputs ofboth the upcounters 2063R1 and 2063R2 is detected by a coincidencedetector 2063R6 in case the output value of the upcounter 2063R1 is not0. It is detected by a 0 detector 2063R4 that the output value of theupcounter 2063R1 is 0. In case the output value of the upcounter 2063R1is 0, the 0 detection result by the 0 detector 2063R4 means the vacancyof the read buffer 2061 and is fed to the central control unit 208. Ifthis state is detected, the central control unit 208 can confirm thatthe read data from the memory 1 has been wholly transferred to thearithmetic circuit 204. The bust counter 2066, as shown in FIG. 8,detects whether or not the given number of continuous data wordstransferred is reached. When this number of words is reached, the outputof the burst counter 2066 is changed to the high level for apredetermined time period. In the read operation of the memory 1, thechange of the output from the burst counter 2066 is fed as a signalmeaning the read complete to an AND gate 2063R5. This AND gate 2063R5detects the read complete of the read buffer 2061, when it receives thesignal meaning the read complete if it is detected by the 0 detector2063R4 that the output of the upcounter 2063R1 is not 0, and transfersthe detected read complete to the central control unit 208. When theread complete of the read buffer 2061 is detected, the central controlunit 208 can confirm that the read data from the memory 1 is whollylatched in the read buffer 2061 so that the central control unit 208 canread the read data from the read buffer 2061 to start the internalarithmetic operation instantly.

[0073]FIG. 10 is a detailed block diagram of one example of a circuitportion relating to the write buffer 2062 in the buffer control circuit2063. The synchronous write address of the write buffer 2062 is producedby an upcounter 2063W2, and the asynchronous write address of the writebuffer 2062 is produced by an upcounter 2063W1. The upcount operation ofthe upcounter 2063W1 is performed in synchronism with the timing atwhich the access clock signal 103 is changed to the high level and atwhich the write buffer write signal from the central control unit 208 isactivated. The upcount operation of the upcounter 2063W2 is performed insynchronism with the operation clock 209 when the write buffer writesignal from the central control unit 208 is activated. Both theupcounters 2063W1 and 2063W2 are cleared to 0 by the high-level outputof the AND gate 2063W3. It is the clearing timing when the outputs ofboth the upcounters 2063W1 and 2063W2 is detected by a coincidencedetector 2063W6 in case the output value of the upcounter 2063W1 is not0. It is detected by a 0 detector 2063W4 that the output value of theupcounter 2063W1 is 0. In case the output value of the upcounter 2063W1is 0, the 0 detection result by the 0 detector 2063W4 means the vacancyof the write buffer 2062 so that the central control unit 208 recognizesthe vacant state of the write buffer 2062. In the write operation of thememory 1, the change of the burst counter 2066 to the high level is fedas a signal meaning the write complete to an AND gate 2063W5. This ANDgate 2063W5 detects the write complete of the write buffer 2062, when itreceives the signal meaning the write complete if it is detected by the0 detector 2063W4 that the output of the upcounter 2063W1 is not 0, andtransfers the detected write complete to the central control unit 208.When the write complete of the write buffer 2062 is detected, thecentral control unit 208 can confirm that the write data to the memory 1in response to the response request from the memory is wholly outputtedfrom the write buffer 2062.

[0074]FIG. 11 shows a buffer memory different from the buffer memory 206shown in FIG. 8. The buffer memory 206, as shown, is equipped with aread/{overscore (write)} buffer 2067 which is shared between the readbuffer 2061 and the write buffer 2062. The buffer control circuit 2063is equipped with a read/{overscore (write)} buffer enable flag 2068which is set with the information concerning which of the read buffer orthe write buffer the read/{overscore (write)} buffer 2067 is to beoperated as. The operation of the read/{overscore (write)} enable flag2068 is controlled according to the instruction coming from the centralcontrol unit 208. The remaining points are similar to those of FIG. 8,and their detail description will be omitted by designating the samecircuit blocks at the same reference characters. This constructioncontributes to a reduction of the chip area.

[0075]FIG. 12 shows an essential portion of an embodiment having acontrol parameter register in place of the memory of FIG. 5.Specifically, there is provided a parameter register 1051 for latchingin a preset table manner the target number of the continuous data wordsto be counted by the burst counter 105 of FIG. 6. This parameterregister 1051 is controlled by the central control unit 208 of the CPU 2to transfer a desired parameter (i.e., the information for specifyingthe number of words for a burst transfer) in a programmable manner. Theremaining constructions are similar to those of FIGS. 5 and 6, and thedetailed description will be omitted by designating the same circuitblocks at the same reference characters. This raises the degree offreedom of data transfer and the flexibility of the control.Incidentally, the parameter register 1051 can be exemplified byconstructing memory stages in a presettable manner in case the memorystages correspond to the number of counted bits.

[0076]FIG. 13 shows an embodiment which has a multi-bit input/outputfunction of ½n bits, for example, for the bit number of the data bus toestablish an interface between the same memory and the CPU 2. In thisembodiment, the CPU 2 is equipped with a plurality of sets of buffermemories 206 and input/output buffer circuits 205. In case the data bus211 has 32 bits whereas the memory 1 has 16 parallel input/output bits,the more significant data bus 211U of 16 bits is coupled through aninput/output buffer circuit 205U to one memory 1U, whereas the lesssignificant data bus 211L is coupled through an input/output buffer 205Lto the other memory IL. The access start signal 200, the read/{overscore(write)} signal 201, the single/{overscore (burst)} signal 202 and theaddress bus 210 are commonly connected with the memories 1U and 1L. Anaccess clock signal 103U is connected with a buffer memory 206U whereasan access clock signal 103L is connected with a buffer memory 206L.Cycle complete signals 104U and 104L are respectively outputted from thememories 1U and 1L and fed to a cycle complete control circuit 2069 totransmit the memory access completes of the two to the access controlcircuit 207.

[0077] The number of parallel input/output bits of the actual memory maybe ×4, ×8, ×9, ×16 or ×18, and the number of parallel data input/outputbits of the CPU may be ×16, ×32, ×36, ×64 or ×72. In order to interfacethe memory and the CPU in a corresponding manner, it is necessary andimportant to provide every bits with the buffer memory, as shown in FIG.13.

[0078]FIG. 14 shows an embodiment of the case in which memories havingdifferent characteristics/functions are mixed to construct the system.In this case, the data transfer can be achieved basically in conformityto an access clock if fine terminal functions or connection conditionsare ignored. Thus, an access clock signal 103-1 of a memory 1-1 and anaccess clock signal 103-2 of a memory 1-2 are coupled through an OR gate300 to the buffer control circuit 2063 outside the CPU 2. Likewise, anaccess complete signal 104-1 of the memory 1-1 and an access completesignal 104-2 of the memory 1-2 are coupled through an OR gate 301 to theaccess control circuit 207 outside the CPU 2. The remaining access startsignal 200, read/{overscore (write)} signal 201, single/{overscore(burst)} signal 202, address bus 210 and data bus 211 are commonlyconnected with the memories 1-1 and 1-2. As a result, the peripheralcircuits such as the memories having the differentcharacteristics/functions can be mixed to construct the system.

[0079]FIG. 15 shows one overall embodiment of a data processing systemusing the CPU 2 and the memory 1, as described in the foregoingembodiments. As the peripheral circuits enabled to perform the datatransfer by a protocol similar to that of the memory (e.g., RAM) 1 ofthe foregoing embodiments, as shown in FIG. 15, there are provided amemory (e.g., ROM) 3; a file control unit 4 to be interfaced with a harddisk drive 41 and a floppy disk drive 42; a display control unit 5 forcontrolling the drawing of a frame buffer 51 and the display of thedrawn data on a monitor 52; a parallel/serial port 6 to be interfacedwith a printer 61 and a keyboard 62; and a communication unit 10 fortransferring data through an antenna and a cable. These peripheralcircuits have their own self-excited oscillators 102 according to theiroperating characteristics so that the data transfer is realized byreturning response requests in response to the access requests from theCPU 2 as in the memory. In FIG. 15, reference numeral 9 designates asystem monitor unit for monitoring a system malfunction and the statusof the supply voltage by means of a watchdog timer. A fast data transferunit 8 is a circuit such as a direct memory access controller, and thebus arbitration with the CPU 2 is accomplished by the bus arbitrator 7.The fast data transfer unit 8 performs the data transfer control likethat of the CPU 2. Numeral 21 designates an external cache memoryintrinsic to the CPU 2 to act as a secondary cache memory for a cachememory 22 in the CPU 2. The data processing system of FIG. 15 isconstructed over a packaging board which is formed with address/databuses 11 and a control bus 12.

[0080] Since the data processing system of FIG. 15 requires no waitstate control for the memories or input/output circuits, neither amemory controller nor an input/output controller is formed on thesubstrate.

[0081] Although our invention has been specifically described inconnection with its embodiments, it should not be limited thereto butcan naturally be modified in various manners without departing from thegist thereof.

[0082] For example, the foregoing embodiments have been described incase the peripheral circuit is exemplified by the memory such as theRAM. However, the peripheral circuit should not be limited thereto butcan be applied not only to the peripheral circuit shown in FIG. 15 butalso to a variety of other peripheral circuits. Moreover, theapplication of such peripheral circuit can cover not only a CPU or adirect memory access controller but also a variety of data processorssuch as a microprocessor, a microcomputer, a single-chip microcomputeror a digital-signal processor.

[0083] On the other hand, the buffer memory should not be limited to theperfect dual port buffer as in the foregoing embodiment but can be usedas if it acts as a dual port for operating a uni-port buffer memory in atime sharing manner. From the standpoint of the chip area of the dataprocessor, on the other hand, the depth (or storage capacity) of thebuffer memory is important, but the much inferior function will have theless contribution to the improvement in the bus rate. Thus, this belongsto the design item which is determined by considering the trade-off fromthe cost performance. Incidentally, the depth of the buffer memory isthought to aid in simplification of the buffer control circuit if it isrestricted to the number of words to be handled by a data transfer ofone time (i.e., the maximum number of words of the burst transfer).

[0084] The effects to be obtained by the representative of the inventiondisclosed herein will be briefly described in the following.

[0085] Specifically, the peripheral circuit is operated in synchronismwith the output signal from its own self-excited oscillator andasynchronously of the operation clock signal of the data processor whichsends an access request to that peripheral circuit. In this relation,the interface between their data is is realized the mutually equivalentaccess requests and the response requests in response to the accessrequest. As a result, a series of data transfer time periods, which havebeen limited in the prior art to an integer times as high as thefundamental operation clock of the data processor, can be determinedaccording to the clock cycle of the response request depending upon theself-excited oscillation frequency which is produced according to thecharacteristics such as the operating speed of the peripheral circuitsuch as the memory.

[0086] From the above discussion, it is easy to realize the datatransfer for the limit time periods of the individual characteristics ofthe peripheral circuit and the data processor. In other words, it ispossible to reduce the unnecessary time period spent for synchronizationwith the operation clock of the data processor, as has been troubled inthe prior art.

[0087] From the above discussion, moreover, the wait state controlcircuit for the interface between the data processor and each of theperipheral circuits can be dispensed with to simplify the circuitconnecting means.

[0088] The data processor equipped on the common chip with the buffermemory to be interfaced with the peripheral circuit can internallyabsorb the difference in the data transfer rate between the internalunit of the data processor and the outside to shorten the time periodfor the sequential standby in the processing of the read data and thewrite data by the access request.

[0089] Thus, the data processing system can be freely constructed byinterfacing the data processor with a plurality of peripheral circuitsof different kinds and by interfacing mutually identical peripheralcircuits having a multi-bit input/output functions of ½n bits for thebit number of the data bus with the data processor.

What is claimed is:
 1. A method of controlling a data transfer between adata processor and its peripheral circuit, comprising the steps of:sending an access request to a peripheral circuit from said dataprocessor; allowing said peripheral circuit to perform an internaloperation according to the access request in synchronism with the outputfrom a self-excited oscillator incorporated therein and in a manner tounderstand the content of said access request; sending a responserequest to said peripheral circuit from said data processor insynchronism with its internal operation in response to said accessrequest; and transferring data to or from said data processor dependingon the type of said access request in synchronism with said responserequest.
 2. A data transfer controlling method according to claim 1 ,wherein said access request contains the information indicating both theperipheral circuit selected as an object to be accessed and the transferdirection of the data, and wherein said response request is a signalvarying in synchronism with the internal operation of said peripheralcircuit.
 3. A peripheral circuit comprising: a cycle timing generatorfor producing an access cycle signal of an internal operation inresponse to an access request from a data processor and on the basis ofan output of a self-excited oscillator; an external terminal foroutputting said access cycle signal as a response request in response tosaid access request; and an internal timing generator for producing aninternal operation timing signal in synchronism with said access cyclesignal.
 4. A peripheral circuit according to claim 3 , wherein saidperipheral circuit is constructed as a memory including: a memory cellarray having a plurality of memory cells arranged in a matrix form; aselector for selecting the memory cells on the basis of an externaladdress signal; a read circuit for reading the data from the selectedmemory cell; and a counter for counting the number of continuous datawords read from said memory cell array on the basis of a change in saidaccess cycle signal, to stop the oscillation of said self-excitedoscillator when the counted result reaches a predetermined count value.5. A peripheral circuit according to claim 4 , wherein said counter hasa parameter register for latching said predetermined count valuepresettably from the outside.
 6. A data processor comprising: an accesscontrol circuit for sending an access request to a peripheral circuit;an input terminal for receiving a response request from the peripheralcircuit in response to said access request; a buffer memory capable ofwriting/reading on the basis of said response request and in synchronismwith an internal operation clock; and an arithmetic circuit and aninput/output buffer circuit connected with said buffer memory.
 7. A dataprocessor according to claim 6 , further comprising: a centralprocessing unit for controlling said access control circuit, said buffermemory, said arithmetic circuit and said input/output buffer circuit. 8.A data processor according to claim 7 , wherein said buffer memoryincludes a counter for detecting the number of continuous read accessrequests to said peripheral circuit from said access control circuit, interms of the number of changes in said response request, whereby saidcentral processing unit receives said detection result as theinformation meaning the complete of the data acquisition by said accessrequest.
 9. A data processor comprising: an access control circuit forsending an access request to a peripheral circuit; an input terminal forreceiving a response request from the peripheral circuit in response tosaid access request; a buffer memory having an asynchronous port forwriting/reading on the basis of said response request, and a synchronousport for writing/reading in synchronism with an internal operationclock; an arithmetic circuit connected with the synchronous port of saidbuffer memory; and an input/output buffer circuit connected with theasynchronous port of said buffer memory for interfacing with externaldevices.
 10. A data processor according to claim 9 , further comprising:a central processing unit for controlling said access control circuit,said buffer memory, said arithmetic circuit and said input/output buffercircuit.
 11. A data processor according to claim 10 , wherein saidbuffer memory includes a counter for detecting the number of continuousread access requests sent to said peripheral circuit from said accesscontrol circuit, in terms of the number of changes in said responserequest, whereby said central processing unit receives said detectionresult as the information meaning the complete of the data acquisitionby said access request.
 12. A data processing system comprising: aperipheral circuit that performs an internal operation according to anaccess request from a data processor and in synchronism with the outputof a self-excited oscillator incorporated therein, and outputs aresponse request to said data processor in synchronism with saidinternal operation in response to said access request; a data processorthat sends an access request to a desired peripheral circuit andreceives a response request from the desired peripheral circuit, therebytransferring data to or from the peripheral circuit depending on thetype of said access request; and a bus connecting said data processorand said peripheral circuit.
 13. A data processing system according toclaim 12 , wherein a plurality of peripheral circuits of different kindsare commonly connected with said bus such that their output terminalsfor response requests share the single input terminal for responserequests of said data processor.